Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. An FPGA may also include various dedicated logic circuits, such as memories, microprocessors, digital clock managers (DCMs), and input/output (I/O) transceivers.
Presently, real time schedulers designs for en-queuing and de-queuing packets, cells, frames, etc. from a memory sub-system are implemented using hardwired circuitry. A weighted round robin scheduler, for example, requires the calculation of the weights while the data is received from the input queues and implementation of a token-based leaky bucket structure to regulate the data flow to the output of the scheduler. This requires the hardwired logic implementing the scheduler to run at frequencies that are several magnitudes higher than the data rate, making such designs impractical to be implemented using a PLD. Accordingly, present scheduling and queuing implementations are application specific integrated circuit (ASIC) solutions, with the ASIC running at more than several hundred megahertz (MHz) and having more than five million gates per design.
Accordingly, there exists a need in the art for a scheduler select multiplexer capable of implementation using a PLD.